Test access port controllers are known in the art. TAP controllers are used to effect communication of test data on and off chip via what is known as a JTAG port. The functions of known TAP controllers are defined by IEEE Standard 1149.1-1990. That Standard defines test logic which can be included in an integrated circuit to provide standardised approaches to testing the interconnections between integrated circuits, testing the integrated circuit itself, and observing or modifying circuit activities during the integrated circuit's "normal" or "user mode" operation.
According to the IEEE Standard, the TAP controller is capable of implementing a variety of different test modes. In each of these test modes, test data is supplied to the chip via an input pin of the TAP controller, and resultant data following the test is supplied off-chip via an output pin of the TAP controller. The resultant data is dependent on the test data and is compared with expected data to check the validity of the test. The input and output pins are referred to respectively as TDI and TDO. Many existing integrated circuits already incorporate a TAP controller of this type with the input and output pins TDI and TDO.
It is one object of the present invention to make use of these pins and the TAP controller to increase the communication facilities of the integrated circuit without multiplexing the pins and thereby violating the standard.
This is particularly useful for diagnostic purposes. That is, where an integrated circuit includes embedded functional circuitry, for example a processor, it is very difficult using existing diagnostic techniques to provide real time non-intrusive monitoring of the functional circuitry. The functional circuitry need not be a processor but could be other functional circuitry, which might include a DMA (Direct Memory Access) engine, or on-chip cache.
In the past, processors (CPUs) were manufactured as a single chip, requiring off-chip access to all their ancillary circuitry, such as memory. As a result, they had a plurality of access pins so that information about the CPU, in particular memory addressing information, was in any event externally available from these access pins.
In addition to memory addressing information, it is useful to be able to obtain status information about the internal state of the processor to ascertain for example such events as interrupts, changes in streams of instructions, setting of flags in various status registers of the CPU, etc.
Nowadays, chips are more complex and contain not only a processor on-chip but also its associated memory and other ancillary circuitry. Often, there may be more than one processor on a chip, or at least one processor and a DMA (Direct Memory Access) engine or EMI (External Memory Interface) for accessing memory associated with the on-chip processor. Thus, it is no longer a simple matter to monitor the operation of the processor because the signals which are normally available off-chip no longer provide a direct indication as to the internal operation of the CPU(s).
With the increasing complexity of software designed to run on integrated circuit CPUs it is increasingly important to adequately test the software. This requires techniques for monitoring operation of the CPU while it executes the software.
It is a particularly onerous requirement that the software be monitored non-intrusively while it is operating in real time.
So-called diagnostic or debugging techniques have been developed in an attempt to achieve this. One existing technique (ICE) involves the manufacture of an emulator board which matches the on-chip hardware and which is connected to it. Thus, the on-chip connections are mapped onto the emulator and are thus accessible on the emulator. However, emulators are complex and expensive to construct and in any event cannot successfully match on-chip communication speeds or conditions. Therefore, it is extremely difficult to truly emulate the on-chip conditions which may prevail.
Another existing technique is to use a logic state analyser (LSA). This is a device connected to the pins of the integrated circuit which monitors continuously the state of all off-chip communications. Each sequentially produced set of states is stored and can then be analysed. Not only is an LSA expensive (although it is less expensive than an emulator), but it requires a large amount of deduction and analysis to derive any useful information from the huge number of sequentially produced state sets which are stored. As it is only possible to analyse the status signals being communicated off-chip, it is inevitably necessary to make some deduction or hypothesis concerning the on-chip situations.
More recently, there have been further developments in an attempt to monitor the operations of "embedded" CPUs. In one integrated circuit, a chain of s-can latches is implemented on-chip to transfer data from the registers of the CPU using the on-chip TAP controller. The process is destructive and therefore it is necessary to read data back into the CPU registers before the CPU can continue operating. Thus, in order to implement this it is necessary to stop the CPU so that the status information from its registers can be extracted. This does not therefore satisfy the requirement that the software should be monitored in real time. In some cases, halting the CPU can actually change the way in which the software operates so that a bug which is visible in real time would not be evident if the CPU were halted at that point.
Moreover, the monitoring process is slow because it is necessary to wait for a test scan to be completed to allow all of the scan data from the CPU registers to be transmitted off-chip.
It is therefore another object of the present invention to allow improved diagnostic procedures to be implemented by increasing the facility for external communications off-chip.